Heres the simulation file I have, must be missing something. To view verilog code and vivado file visit. S0 : if (main = 0 & side = 1 ) begin if (count1 > 0 ) beginĬount2 = delay15 end default : state <= S0 endcase end always ( * ) begin case (state ) Please like and subscribe our channel for any latest update. S3 : state <= S0 default : state <= S0 endcase end always ( * ) begin case (state ) ) reg state parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11 always ( posedge clk ) begin case (state ) Module Traffic_Signal ( input main, input side, input wire clk, output reg MG, //Mainstreet Green output reg MY, //Mainstreet Yellow output reg MR, //Mainstreet Red output reg SG, output reg SY, output reg SR
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